A programmable logic circuit, also referred to as field programmable gate array (FPGA) is an off the shelf integrated logic circuit which can be programmed by the user to perform logic functions. Circuit designers define the desired logic functions and the circuit is programmed to process the signals accordingly. Depending on logic density requirements and production volumes, programmable logic circuits are superior alternatives in terms of cost and time to market. A typical programmable logic circuit is composed of logic cells where each of the logic cells can be programmed to perform logic functions on its input variables. Additionally, interconnect resources are provided throughout the programmable logic circuit which can be programmed to conduct signals from outputs of logic cells to inputs of logic cells according to user specification.
As technology progresses to allow for larger and more sophisticated programmable logic circuits, both the number of logic cells and the required interconnect resources increases in the circuit. Competing with the increased number of logic cells and interconnect resources is the need to keep the circuit size small. One way to minimize the required circuit size is to minimize the interconnect resources while maintaining a certain level of connectivity. Therefore, it can be seen that as the functionality implemented on the chip increases, the interconnection resources required to connect a large number of signals can be quickly exhausted. The trade-offs are either to provide for a lower utilization of logic cells in a circuit while keeping the circuit size small or to provide more routing resources that can increase the circuit size dramatically.
There has been a progression of increasingly complex connection styles over the last forty years in the field of programmable logic circuits. L. M. Spandorfer in 1965 describes possible implementation of a programmable logic circuit using neighborhood interconnection, and connections through multiple conductors using switches in a Clos network. R. G. Shoup in his PhD thesis of 1970 describes both the use of a neighborhood interconnect and the use of a bus for longer distance interconnect.
Freeman in U.S. Pat. No. 4,870,302 of 1989 describes a commercial implementation of a FPGA using neighborhood interconnects, short (length one, called single) distance interconnects, and global lines for signals such as clocks. The short distance interconnects interact with the inputs and outputs of logic cells where each input is connected through switches to every short wire neighboring to a logic cell and horizontal and vertical short wires connect through a switch box in a junction. El Gamal et al. in U.S. Pat. No. 4,758,745 introduces segmented routing where inputs and outputs of logic cells interact with routing segments of different lengths in one dimension.
Peterson et al. in U.S. Pat. No. 5,260,610 and Cliff et al. in U.S. Pat. No. 5,260,611 introduce a local set of conductors interfacing with a set of logic elements where every input of the logic elements is connected, through switches, to every local conductor in the set; additional chip length conductors are introduced both horizontally and vertically where the horizontal conductor can connect to the vertical conductors and the horizontal conductors connect to multiple local conductors. In U.S. Pat. No. 4,870,302, U.S. Pat. No. 4,758,745, U.S. Pat. No. 5,260,610, and U.S. Pat. No. 5,260,611, the input conductor of a logic cell has full connections to the set of local conductors (e.g. for n-inputs and k-local conductors, there is n×k switches connecting the inputs to the local conductors. A multiplexer (MUX) scheme may also be used so that the number of transistors is reduced). In U.S. Pat. No. 4,870,302, U.S. Pat. No. 4,758,745, U.S. Pat. No. 5,260,610, and U.S. Pat. No. 5,260,611, the general interconnect resources are limited to one or two different lengths (i.e. singles of U.S. Pat. No. 4,870,302, local and chip length in U.S. Pat. No. 5,260,610 and U.S. Pat. No. 5,260,611) or limited in one dimension (i.e. different lengths horizontally in U.S. Pat. No. 4,758,745, local vertically in U.S. Pat. No. 5,260,610 and U.S. Pat. No. 5,260,611).
Camarota et al. in U.S. Pat. No. 5,144,166 and Kean in U.S. Pat. No. 5,469,003 introduce a routing scheme with more than two different lengths in both dimensions with limitations in the reach of those conductors. While U.S. Pat. No. 5,144,166 allows each wire to be selectively driven by more than one possible driving source, U.S. Pat. No. 5,469,003 is limited to be unidirectional in that each wire is hardwired to a multiplexer output. The connectivity provided in both U.S. Pat. No. 5,144,166 and U.S. Pat. No. 5,469,003 are very low, based on the premises that either connections are neighborhood or relatively local, or logic cells itself can be used as interconnection resources instead of performing logic functions. Ting in U.S. Pat. No. 5,457,410, U.S. Pat. No. 6,507,217, U.S. Pat. No. 6,051,991 and U.S. Pat. No. 6,597,196 described a multiple level architecture where multiple lengths of conductors interconnect through switches in a hierarchy of logic cells.
Young et al. in U.S. 2001/0007428 and U.S. Pat. No. 5,914,616 describe an architecture with multiple lengths of wires in two dimensions (three in each dimension), where for short local connections, a near cross-bar scheme is used where a set of logic cells outputs are multiplexed to a reduced set of output ports which then interface to other interconnect resources. The longer wires generally fan-in into shorter length wires in a respective dimension. Reddy et al. in U.S. Pat. No. 6,417,694 discloses another architecture where inter-super-region, inter-region, and local conductors are used. A cross-bar scheme is used at the lowest level (using MUXs) for the local wires to have universal access to the inputs of the logic elements. Reddy et al. in U.S. Pat. No. 5,883,526 discloses various schemes having circuit reduction techniques in the local cross-bar.
Reblewski et al. in U.S. Pat. No. 6,594,810 describes an architecture building a programmable logic circuit using crossbar devices recursively. Wong in U.S. Pat. No. 6,693,456 and U.S. Pat. No. 6,940,308 use Benes switching networks as the interconnection fabric for programmable logic circuit.
At the base level of circuit hierarchy, multiple-input Look Up Table (LUT) logic cells are commonly used. There are two advantages in using a LUT as the base logic cell. One advantage is that the LUT allows programmable implementation of any Boolean functions having up to the multiple-input and one output. Another advantage is that the multiple inputs are interchangeable and logically equivalent. Hence, it does not matter which signal connecting to which input pin of the LUT for the LUT to function correctly as long as those signals connect to the respective inputs of the LUT.
A common problem to be solved in any programmable logic circuit is that of interconnectivity, namely, how to connect a first set of conductors or pins carrying signals to a second multiple sets of conductors to receive those signals where the logic cells originating the signals and the logic cells receiving the signals are spread over a wide area in an integrated circuit (i.e., M number of outputs from M or less number of logic cells where one or more outputs of each logic cells connects to inputs of one or more logic cells). A conventional solution is to use a cross bar switch where every conductor of the first set is connectable to every conductor in the second multiple sets of conductors directly through a switch. Unfortunately, this approach is impractical in most cases. Prior solutions in one degree or another try to divide the connectivity problem into multiple pieces using a divide and conquer strategy where local clusters of logic cells are interconnected and extended to other clusters of logic, either through extensions of local connections or using longer distance connections. These prior interconnect schemes are ad hoc and mostly based on empirical experiences. A desired routing model or interconnect architecture should enable or guarantee full connectivity for a large number of inputs and outputs over a large part of the circuit all the time.
U.S. Pat. No. 6,975,139, U.S. Pat. No. 7,256,614 and U.S. Pat. No. 7,417,457 by the present inventors describe one type of switching network (L-SN) with L levels of intermediate conductors which uses Ei=[1:L+1](I[i−1]×D[i]) number of switches and L levels of intermediate conductors of I[i] number of conductors, having D[i] sets of conductors for i=[1:L] to connect a 0-the level of conductors of I[0] number of conductors to a (L+1)-th level of conductors of (D[L+1]×Πi=[1:L]D[i]) number of conductors consisting of D[L+1] sets of conductors. The L-SN can be used as part of an interconnection fabric for a switching system, a router or a programmable logic circuit with much reduced switch counts and the number of switches used in the switching network is determined by a mathematical relations of the sizes of the 0-th level of conductors of I[0] number of conductors, the L levels of intermediate conductors and the size of the (L+1)-th level of conductors of (D[L+1]×Πi=[1:L]D[i]) number of conductors consisting of D[L+1] sets of conductors. The switching network, when limited to be a 1-SN or at the last intermediate stage or level in the conventional designs, can have certain routing limits when at least one multicasting signal is logically grouped together with other signals from the first set of conductors in a skewed distribution. Thus, it is desirable to have an enhanced permutable switching network for programmable logic circuits where the routability or interconnectivity may be enhanced in the presence of multicasting signals independent of signal distribution while the cost of interconnections remains low in terms of number of switches and the software efforts in determining a place and route and the circuit layout implementation may be simplified.
One type of an L-level switching network (L-SN) of the conventional design was first described by the present inventors in U.S. Pat. No. 6,975,139, U.S. Pat. No. 7,256,614 and U.S. Pat. No. 7,417,457 in which the L-SN has (L+2) levels of conductors with L-level(s) of intermediate conductors of I[i] number of conductors consisting of D[i] sets of conductors for i=[1:L], L≧1 and Σi=[1:L+1](I[i−1]×D[i]) number of switches where the 0-th level of pins or conductors of I[0] number of pins or conductors selectively couple to the (L+1)-th level of pins or conductors of (D[L+1]×Πj=[1:L]D[j]) number of pins or conductors consisting of D[L+1] sets of pins or conductors through the L level(s) of intermediate conductors and Σi=[1:L+1](I[i−1]×D[i]) number of switches of the L-SN. A variable, DS[i], is defined as DS[i]=(I[i−1]/I[i])×D[i] for i=[1:L+1]. A DS[i]-tuple is DS[i] number of conductors of the (i−1)-th level of conductors with the characteristics that the DS[i]-tuple selectively couple to one conductor, through a respective DS[i] number of switches, in each of the D[i] sets of conductors of the i-th level of conductors of the L-SN for i=[1:L+1]. Additionally, in the L-SN, the I[i−1] number of conductors of the (i−1)-th level can be organized into (I[i−1]/DS[i]) groups of DS[i]-tuples for i=[1:L+1].
As an illustration of the conventional designs, FIG. 1A shows one embodiment of the switch couplings between the first two levels of conductors in the conventional L-SN of U.S. Pat. No. 6,975,139, U.S. Pat. No. 7,256,614 and U.S. Pat. No. 7,417,457, where L=2: the 0-th level of conductors of I[0]=36 number of conductors, [1:36], selectively couple to the first level of conductors of I[1]=36 number of conductors consisting of D[1]=2 sets of (intermediate) conductors, {[101:118], [119:136]}; not every conductor of I[1] number of conductors are labeled in the embodiment of FIG. 1A, and for purpose of illustration, those conductors are assumed to be consecutively labeled, thus the first set of conductors of the D[1]=2 sets has (I[1]/D[1])=18 conductors, [101:118], where the I[0] number of conductors [1:36] selectively couple to the eighteen conductors [101:118] of the first set of the first level of conductors through I[0]=36 number of switches; and the D[1]-th set has eighteen conductors [119:136] where the I[0] number of conductors [1:36] selectively couple to the eighteen conductors [119:136] of the D[1]-th set of the first level of conductors through I[0]=36 number of switches. A DS[1]-tuple of the embodiment of FIG. 1A is of size two which is any of the two consecutive conductors such as [1,2], [3,4], etc. of the I[0] number of conductors [1:36]; a DS[2]-tuple is of size three which is any of the three consecutive conductors such as [101:103], [104:106], etc. of the I[1] number of conductors [101:136].
FIG. 1B illustrates one embodiment of the switch couplings between the next two levels of conductors of the 2-SN embodiment of FIG. 1A; the first level of conductors of I[1] number of conductors selectively couple to each of the D[2]=3 sets of conductors of I[2]=36 number of conductors where each of the D[2] sets has twelve conductors: [141:152], [153:164] and [165:176]. Again, not every conductors of I[2] of FIG. 1B are labeled and they are assumed to be consecutively labeled; thus the I[1] number of conductors [101:136] selectively couple to each of the D[2] sets of twelve conductors: [141:152], [153:164] and [165:176] through, respectively, I[1]=36 number of switches. Since L=2, D[3]=D[L+1]=Πj=[1:L]D[j]=6 and DS[3]=(I[2]/I[3])×D[3]=6, each of the six consecutively labeled conductors of I[2] of FIG. 1B such as [141:146], [147:152], etc. would be a DS[3]-tuple.
FIG. 1C illustrates one embodiment of the switch couplings between the last two levels of conductors of the 2-SN embodiment of FIG. 1A and FIG. 1B; the second level of conductors of I[2] number of conductors selectively couple to each of the D[3]=6 sets of conductors of I[3]=36 number of conductors where each of the D[3] sets has six conductors: [181:186], [187:192], [193:198], [199:204], [205:210] and [211:216]. Again, not every conductors of I[3] of FIG. 1C are labeled and they are assumed to be consecutively labeled; thus the I[2] number of conductors [141:176] selectively couple to each of the D[3] sets of six conductors: [181:186], [187:192], [193:198], [199:204], [205:210] and [211:216] through, respectively, I[2]=36 number of switches.
It is readily observed that any of the conventional L-SN described above can be drawn such that the DS[i] number of conductors of each DS[i]-tuple can be logically labeled as being consecutive for i=[1:L+1] as illustrated in FIG. 1A through FIG. 1C.
In the embodiment of FIG. 1B, assuming conductor or net 101 carries signal connection specification (1, 2) indicating destination connection specifications to F1 and F2 modules of FIG. 1C of the L-SN, net 102 has connection specifications of (2, 3), net 103 has connection specifications of (1, 3), net 104 has connection specifications of (1), net 105 has connection specifications of (3) and net 106 has connection specifications of (2, 3); the six nets [101:106], or the two DS[i]-tuples {[101:103], [104:106]}, has a total of ten connections to the pins of the [F1:FK] modules with three connections to F1, three connections to F2 and four connections to F3. At most nine connections can be made in the 2-SN example of FIG. 1B and FIG. 1C, illustrated by the blackened squares indicating activating the switches connecting the conductors where one of the connection specifications (3), connecting to a pin of F3, of net 106 can not be made in the six nets example illustrated in FIG. 1B and FIG. 1C.
Specifically, in FIG. 1B and FIG. 1C, net 101 connects to 141 which then connects to 181 of F1 and 187 of F2 through the respective switches indicated by the blackened squares, net 102 connects to 153 which then connects to 189 of F2 and 195 of F3 through the respective switches indicated by the blackened squares, net 103 connects to 165 which then connects to 185 of F1 and 197 of F3 through the respective switches indicated by the blackened squares, net 104 connects to 154 which then connects to 183 of F1 through the respective switches indicated by the blackened squares, net 105 connects to 142 which then connects to 193 of F3 through the respective switches indicated by the blackened squares, net 106 connects to 166 which then connects to 191 of F2 through the respective switches indicated by the blackened squares while the connection to F3 of net 106 can not be completed.
Thus generally the six conductors [101:106] of the (i−1)-th level of conductors can be considered as “source-conductors” or the two DS[i]-tuples {[101:103], [104:106]}can be considered as “source-tuples” where the “source-conductors” or the “source-tuples” selectively couple to six conductors of the i-th level of conductors (141, 142, 153, 154, 165, 166) where those conductors can be considered as the “coupling-conductors” for i=2 in FIG. 1B.
The six nets routing example illustrated using FIG. 1B and FIG. 1C with one pin connection left un-routed can be resolved if the connection specifications are not congested together: this can either be accomplished by changing the switch coupling patterns between two consecutive levels of conductors different from the L-SN constructs or by managing the distributions upstream to prevent locally skewed congestions downstream.